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19-6261; rev 1; 12/12 benefits and features s ieee 802.3af compliant s poe class 1/class 2 classification s simplified wall adapter interface s intelligent mps s sleep and ultra-low-power mode (max5986a/ max5986b) s efficient, integrated dc-dc converter (with integrated switches) s 8.7v to 60v wide input voltage range s 3.0v to 14v programmable output voltage range s internal compensation s fixed 214khz/275khz switching frequency s frequency foldback for high-efficiency light- load operation s built-in output-voltage monitoring s open-drain reset output (MAX5987A) s protects against overload, output short circuit, output overvoltage, and overtemperature s hiccup-mode runaway current limit s back-bias capability to optimize the efficiency s integrated tvs diode withstands cable discharge event (cde) s internal ldo regulator with up to 100ma load (MAX5987A) s fixed 3.3v or adjustable output voltage through an external resistive divider s 49ma (typ) inrush current limit s pass 2kv, 200m cat-6 cable discharge event general description the max5986a/max5986b/MAX5987A provide a com - plete power-supply solution as ieee ? 802.3af-compliant class 1/class 2 powered devices (pds) in a power-over- ethernet (poe) system. the devices integrate the pd interface with an efficient dc-dc converter, offering a low external part count pd solution. the MAX5987A includes a low-dropout regulator and the max5986a/max5986b include sleep and ultra-low power modes. the pd interface provides a detection signature and a class 1/class 2 classification signature with a single external resistor. the pd interface also provides an isolation power mosfet, a 60ma (max) inrush current limit, and a 201ma (max5986a) or 323ma (max5986b/ MAX5987A) operating current limit. the integrated step-down dc-dc converter uses a peak current-mode control scheme and provides an easy-to- implement architecture with a fast transient response. the step-down converter operates in a wide input volt - age range from 8.7v to 60v and supports up to 3.84w (max5986a) or 6.49w (max5986b/MAX5987A) of input power. the max5986a operates at a fixed 275khz switching frequency, while the max5986b/MAX5987A operate at a fixed 215khz switching frequency. the dc-dc converter operates at a fixed 275khz switch - ing frequency, with an efficiency-boosting frequency foldback that reduces the switching frequency by half at light loads. the devices feature an input undervoltage-lockout (uvlo) with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition during power-on/-off conditions. the devices also feature overtemperature shutdown, short-circuit protection, output overvoltage protection, and hiccup current limit for enhanced perfor - mance and reliability. the max5986a/max5986b/MAX5987A are available in a 16-pin, 5mm x 5mm, tqfn power package and operate over the -40c to +85c temperature range. applications ieee 802.3af-powered devices ip phones wireless access nodes ip security cameras wimax ? base stations ieee is a registered service mark of the institute of electrical and electronics engineers, inc. wimax is a registered certification mark and registered service mark of wimax forum. ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max5986a/MAX5987A.related . max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.
2 junction-to-ambient thermal resistance ( q ja ) .............. 35c/w junction-to-case thermal resistance ( q jc ) .................. 2.7c/w absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 2) note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . (all voltages referenced to gnd, unless otherwise noted.) v dd to gnd ........................................................... -0.3v to +70v (100v, 100ms, r test = 3.3k) (note 1) v cc , wad, rref to gnd ........................ -0.3v to (v dd + 0.3v) aux, ldo_in, led to gnd .................................... -0.3v to 16v ldo_out to gnd .............................. -0.3v to (ldo_in + 0.3v) ldo_fb to gnd ...................................................... -0.3v to +6v lx to gnd ................................................ -0.3v to (v cc + 0.3v) ldo_out, vdrv, fb, reset , wk, sl , ulp , mps, class2 to gnd .............................................................. -0.3v to +6v vdrv to v dd ............................................ -0.3v to (v dd + 0.3v) pgnd to gnd ...................................................... -0.3v to +0.3v lx total rms current ........................................................... 1.6a continuous power dissipation (t a = + 70 n c) tqfn (derate 28.6mw/ n c above +70 n c) .............. 2285.7mw operating temperature range .......................... -40 n c to +85 n c junction temperature .................................................... .+150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ............................... .+300 n c soldering temperature (reflow) ...................................... +260 n c note 1: see figure 1, test circuit . electrical characteristics (v dd = 48v, r sig = 24.9k, led, v cc , sl , ulp , wk , reset , ldo_out unconnected, wad = ldo_en = ldo_in = pgnd = gnd, c1 = 68nf, c2 = 10f, c3 = 1f (see figure 3), v fb = v aux = 0v, lx unconnected. v class2 = 0v, v mps = 0v (except for max5986a). all voltages are referenced to gnd, unless otherwise noted. t a = t j = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units power device (pd) interface detection mode input offset current i offset v vdd = 1.4v to 10.1v (note 4) 10 f a effective differential input resistance dr v vdd = 1.4v to 10.1v with 1v step, (note 5) 23.95 25.5 k i classification mode classification enable threshold v th,cls,en v dd rising 10.2 11.5 12.5 v classification disable threshold v th,cls,dis v dd rising 22 23 23.8 v classification stability time 2 ms classification current i class v dd = 12.6v to 20v class2 = gnd 9.12 10.5 11.88 ma class2 = vdrv 16.1 18 20.9 power mode v dd supply voltage range v dd 60 v v dd supply current i dd v dd = 60v 3.6 4.5 ma v dd turn-on voltage v on v dd rising max5986a/b 34.3 35.7 37.6 v MAX5987A 37.2 38.7 40 v dd turn-off voltage v off v dd falling 30 31.4 v max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
3 electrical characteristics (continued) (v dd = 48v, r sig = 24.9k, led, v cc , sl , ulp , wk , reset , ldo_out unconnected, wad = ldo_en = ldo_in = pgnd = gnd, c1 = 68nf, c2 = 10f, c3 = 1f (see figure 3), v fb = v aux = 0v, lx unconnected. v class2 = 0v, v mps = 0v (except for max5986a). all voltages are referenced to gnd, unless otherwise noted. t a = t j = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units v dd turn-on/off hysteresis v hyst_uvlo (note 6) max5986a/b 3.4 4.2 v MAX5987A 7.2 v dd deglitch time t off_dly v dd falling from 40v to 20v (note 5) max5986a 116 f s max5986b/ MAX5987A 150 inrush to operating mode delay t delay t delay = time from a (v dd - v cc ) 1.5v to 0v max5986a 90 ms max5986b/ MAX5987A 123 isolation power mosfet on-resistance r on_iso i vcc = 100ma t j = +25 n c 1.2 i t j = +85 n c 1.5 maintain power signature (mps = vdrv) poe mps current rising threshold i mps_rise max5986b/MAX5987A only 18 28.7 40 ma poe mps current falling threshold i mps_fall max5986b/MAX5987A only 14 24 35 ma poe mps current threshold hysteresis i mps_hys max5986b/MAX5987A only 4.3 ma poe mps output average current i mps_ave max5986b/MAX5987A only 4.8 ma poe mps peak output current i mps_peak max5986b/MAX5987A only 10 12.6 ma poe mps time high t mps_high max5986b/MAX5987A only 95 ms poe mps time low t mps_low max5986b/MAX5987A only 190 ms current limit inrush current limit i inrush during initial turn-on period, v dd - v cc = 4v, measured at v cc 39 49 60 ma current limit during normal operation i lim after inrush completed, v cc = v dd C 1.5v, measured at v cc max5986a 175 201 226 ma max5986b/ MAX5987A 290 323 360 wad detection rising threshold v wad_rise (note 9) 8.8 v wad detection falling threshold v wad_fall (note 9) 5.8 v wad detection hysteresis 0.6 v wad input current i wad v wad = 24v 125 f a max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
4 electrical characteristics (continued) (v dd = 48v, r sig = 24.9k, led, v cc , sl , ulp , wk , reset , ldo_out unconnected, wad = ldo_en = ldo_in = pgnd = gnd, c1 = 68nf, c2 = 10f, c3 = 1f (see figure 3), v fb = v aux = 0v, lx unconnected. all voltages are referenced to gnd, unless otherwise noted. t a = t j = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units logic class2, mps voltage rising threshold max5986b/MAX5987A only 2.9 v class2, mps voltage falling threshold max5986b/MAX5987A only 0.4 v reset output voltage low (MAX5987A only) i sink = 1ma 0.2 v reset , class2, mps leakage max5986b/MAX5987A only -10 +10 f a internal regulator with back bias v aux input voltage range v aux inferred from v aux input current 4.75 14 v v aux input current v aux from 4.75v to 14v 0.65 3.1 ma v drv output voltage 4.2 5.5 v sleep mode max5986a/max5986b) wk and ulp logic threshold v th v wk falling and v ulp rising and falling 1.6 2.9 v sl logic threshold falling 0.55 0.8 v sl current v sl = 0v 62.5 f a led current amplitude i led r sl = 60.4k i , v led = 6.5v 9.2 10.6 12 ma r sl = 30.2 k i , v led = 6.5v 19.2 21.2 23.5 r sl = 30.2 k i , v led = 3.5v 21.2 led current programmable range 10 20 ma led current with grounded sl v sl = 0v 20.6 26.4 31.4 ma led current frequency f iled sleep and ultra-low power modes 250 hz led current duty cycle d iled sleep and ultra-low power modes 25 % v dd current amplitude i vdd sleep mode, v led = 6.5v 10 12 14.5 ma internal current duty cycle d ivdd sleep and ultra-low power modes 75 % internal current enable time t mps ultra-low power mode 76 87 98 ms internal current disable time t mpdo ultra-low power mode 205 235 265 ms thermal shutdown thermal shutdown threshold t sd t j rising max5986a 143 n c max5986b/ MAX5987A 151 thermal shutdown hysteresis t sd,hys 16 n c max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
5 electrical characteristics (continued) (v dd = 48v, r sig = 24.9k, led, v cc , sl , ulp , wk , reset , ldo_out unconnected, wad = ldo_en = ldo_in = pgnd = gnd, c1 = 68nf, c2 = 10f, c3 = 1f (see figure 3), v fb = v aux = 0v, lx unconnected. all voltages are referenced to gnd, unless otherwise noted. t a = t j = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units ldo (MAX5987A) input voltage range inferred from line regulation 4.5 14 v output voltage ldo_fb = v drv 3.3 v max output voltage setting with external divider to ldo_fb 5.5 v ldo fb regulation voltage 1.2 1.227 1.25 v ldo fb leakage current 1 f a dropout v ldo _ in = 5v, v ldo_fb = v drv , i load = 80ma 300 mv load regulation i load from 1ma to 80ma 0.5 mv/ma line regulation vldo_in from 4.5v to 14v 1.4 mv/v overcurrent protection threshold i ovc 85 ma ldo_fb rising threshold 3.2 3.7 v ldo_fb hysteresis 2.3 2.4 v dc-dc converter input supply v dd voltage range v dd,rising v cc = v dd = v wad - 0.3v, rising max5986a 8.7 60 v max5986b/ MAX5987A 8 60 v dd,falling v cc = v dd = v wad - 0.3v, falling max5986a 7.3 60 max5986b/ MAX5987A 7.7 60 power mosfets high-side pmos on-resistance r dson-h i lx = 0.5a (sourcing) 0.54 i low-side nmos on-resistance r dson-l i lx = 0.5a (sinking) 0.16 i lx leakage current i lx-lkg v dd = v cc = 28v, v lx = (v pgnd + 1v) to (v cc - 1v) -5 +5 f a soft-start (ss) soft-start time t ss-th max5986a 7.45 ms max5986b/MAX5987A 10 feedback (fb) fb regulation voltage v fb-rg 1.203 1.225 1.252 v max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
6 electrical characteristics (continued) (v dd = 48v, r sig = 24.9k, led, v cc , sl , ulp , wk , reset , ldo_out unconnected, wad = ldo_en = ldo_in = pgnd = gnd, c1 = 68nf, c2 = 10f, c3 = 1f (see figure 3), v fb = v aux = 0v, lx unconnected. all voltages are referenced to gnd, unless otherwise noted. t a = t j = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) fb input bias current i fb v fb = 1.224v 10 200 na parameter symbol conditions min typ max units output voltage output voltage range v out max5986a/MAX5987A 3.0 5.6 v max5986b 5.4 14 cycle by cycle overvoltage protection v out-ov rising (note 7) 100.5 100.3 108 % falling (note 7) 98.5 internal compensation network compensation network zero- resistance r zero 200 k i compensation network zero- capacitance c zero 150 pf current limit peak current-limit threshold i peak-limit max5986a 1.45 64 a max5986b class2 = gnd 0.75 0.81 class2 = vdrv 0.85 0.94 MAX5987A class2 = gnd 1.45 1.64 class2 = vdrv 1.66 1.79 runaway current-limit threshold i runaway- limit max5986a 1.9 a max5986b class2 = gnd 0.93 class2 = vdrv 1.07 MAX5987A class2 = gnd 1.9 class2 = vdrv 2.2 valley current-limit threshold i valley- limit max5986a/MAX5987A 1.5 a max5986b 0.75 zx threshold i zx 25 ma timings switching frequency f sw max5986a 245 275 305 khz max5986b/MAX5987A 190 215 238 frequency foldback f sw-fold max5986a 122.5 137.5 152.5 khz max5986b/MAX5987A 95 107.5 119 consecutive zx events for entering foldback 8 events consecutive zx events for exiting foldback 8 events max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
7 electrical characteristics (continued) (v dd = 48v, r sig = 24.9k, led, v cc , sl , ulp , wk , reset , ldo_out unconnected, wad = ldo_en = ldo_in = pgnd = gnd, c1 = 68nf, c2 = 10f, c3 = 1f (see figure 3), v fb = v aux = 0v, lx unconnected. all voltages are referenced to gnd, unless otherwise noted. t a = t j = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) note 3: all devices are 100% production tested at t a = +25c. limits over temperature are guaranteed by design. note 4: the input offset current is illustrated in figure 2. note 5: effective differential input resistance is defined as the differential resistance between v dd and gnd, see figure 2. note 6: a 20v glitch on input voltage, which takes v dd below v on shorter than or equal to t off_dly does not cause the device to exit power-on mode. note 7 referred to feedback regulation voltage. note 8: referred to ldo feedback regulation voltage. note 9: the wad detection rising and falling thresholds control the isolation power mos transistor. to turn the dc-dc on in wad mode, the wad must be detected and the v dd must be within the v dd voltage range. v out undervoltage trip level to cause hiccup v out-hicf after soft-start completed (note 7) 55 60 65 % parameter symbol conditions min typ max units hiccup timeout max5986a 120 ms max5986b/MAX5987A 154 minimum on-time t on-min 113 140 ns lx dead time 14 ns reset (MAX5987A) v fb threshold for reset assertion v fb-okf v fb falling (note 7) 87 90 93 % v fb threshold for reset deassertion v fb-okr v fb rising (note 7) 91.5 95 98 % v ldo_fb threshold for reset assertion v ldo_fb-okf v ldo_fb falling, ldo_fb = v drv (note 8) 90 % v fb threshold for reset deassertion v fb rising 95 % v ldo_fb threshold for reset assertion v fb falling 90 % v ldo_fb threshold for reset deassertion v fb rising 95 % for reset deassertion delay 4.8 ms reset output voltage low i sink = 1ma 0.1 v reset leakage current 10 f a max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
8 typical operating characteristics (t a = +25c, unless otherwise noted.) figure 2. effective differential resistance and offset current figure 1. max5986a/MAX5987A internal tvs test setup detection current vs. input voltage max5986a toc01 input voltage (v) detection current (ma) 8.9 7.4 5.9 4.4 2.9 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 1.4 10.1 quiescent current vs. supply voltage (ultra-low power mode) max5986a toc02 supply voltage (v) quiescent current (ma) 55 50 45 40 2.75 3.00 3.25 3.50 3.75 4.00 2.50 35 60 signature resistance vs. supply voltage max5986a toc03 supply voltage (v) differential resistance (ki) 7.4 5.9 4.4 2.9 23 24 25 26 27 28 22 1.4 10.1 8.9 input offset current vs. input voltage max5986a toc04 supply voltage (v) offset current (a) 7.4 5.9 4.4 2.9 -2 -1 0 1 2 3 -3 1.4 10.1 8.9 i in i ini + 1 i ini i offset dr i 1v v ini v ini + 1 i offset = i ini - v ini dr i dr i = (v ini + 1 - v ini ) = 1v (i ini + 1 - i ini ) (i ini + 1 - i ini ) v in evaluation board 1ms /1 0ms / 100ms r test max5986a 100 v max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
9 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) classification settling time max5986a toc06 v dd 10v/div gnd i dd 10ma /div 0ma 400s/div classification current vs. input voltage max5986a toc05 input voltage (v) classification current (ma) 18.6 17.1 15.6 14.1 10.42 10.44 10.46 10.48 10.50 10.52 10.54 10.56 10.58 10.60 10.40 12.6 20.0 led current vs. r sl max5986a toc08 r sl (ki) led current (ma) 70 60 50 40 30 20 12 18 20 24 28 8 10 80 led current vs. led voltage max5986a toc09 led voltage (v) led current (ma) 5.25 3.50 1.75 10 15 20 25 5 0 7.00 r sl = 30.2ki r sl = 60.4ki efficiency vs. load current (max5986a, v out = 5v) max5986a toc10 load current (ma) efficiency (%) 0.8 0.9 1.0 0.7 0.6 0.4 0.5 0.2 0.3 0.1 60 65 70 75 80 85 90 95 100 0 v in = 12v v in = 36v v in = 57v v in = 48v inrush current limit vs. v cc voltage max5986a toc07 v cc (v) inrush current (ma) 42 36 30 24 18 12 6 44 48 52 56 60 40 04 8 max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
10 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) 5v load transient (0% to 50%) max5986a toc13 v out ac-coupled 50mv/div i out 500ma /div 0a 100s/div dc-dc converter startup i out = 0a max5986a toc15 v out 1v/div v gnd 2ms/div 5v load transient (50% to 100%) max5986a toc14 v out ac-coupled 50mv/div i out 500ma /div 0a 100s/div dc-dc converter startup r out = 6.67i max5986a toc16 v out 1v/div v gnd 2ms/div efficiency vs. load current (max5986b, v out = 12v) max5986a toc11 load current (ma) efficiency (%) 0.7 0.6 0.4 0.5 0.2 0.3 0.1 60 65 70 75 80 85 90 95 100 0 v in = 36v v in = 48v v in = 57v efficiency vs. load current (MAX5987A, v out = 5v) max5986a toc12 load current (a) efficiency (%) 1.0 0.9 0.8 0.7 0.5 0.6 0.2 0.3 0.4 0.1 60 65 70 75 80 85 90 95 100 0 v in = 12v v in = 36v v in = 48v v in = 57v max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
11 pin description pin configurations pin name function max5986a max5986b MAX5987A 1 1 1 aux auxiliary voltage input. auxiliary input to the internal regulator (vdrv). connect aux to the output of the buck converter if the output voltage is greater than 4.75v to back bias the internal circuitry and increase efficiency. connect to a clean ground when not used. 2 2 2 lx inductor connection. inductor connection for the internal dc-dc converter. 3 3 led led driver output. in sleep mode, led sources a periodic current (i led ) at 250hz with 25% duty cycle. 3 ldo_in ldo input voltage. connect ldo_in to output when used, otherwise connect to gnd. connect a minimum 1 f f bypass capacitor between ldo_in and gnd. 4 4 wk wake mode enable input. wk has an internal 50k i pullup resistor to the internal 5v bias rail. a falling edge on wk brings the device out of sleep mode and into the normal operating mode (wake mode). 4 ldo_out ldo output voltage. connect a minimum 1 f f output capacitor between ldo_out and gnd. 5 5 5 fb feedback. feedback input for the dc-dc buck converter. connect fb to a resistive divider from the output to gnd to adjust the output voltage. 15 16 14 13 6 5 7 lx wk 8 aux gnd (mps) ulp wad 12 v cc 4 12 11 9 pgnd rref *ep *ep *exposed pad, connect to gnd ( ) applies to max5986b *exposed pad, connect to gnd sl vdrv gnd fb + led gnd (class2) 3 10 v dd tqfn max5986a max5986b top view 15 16 14 13 6 5 7 lx ldo_out 8 aux reset gnd wad 12 v cc 4 12 11 9 pgnd rref ldo_fb vdrv gnd fb + ldo_in gnd 3 10 v dd tqfn MAX5987A max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
12 pin description (continued) pin name function max5986a max5986a max5986a 6, 10, 11 6 6 gnd ground. reference rail for the device. it is also the quiet ground for all voltage reference (e.g., fb is referenced to this gnd). 7 7 7 vdrv internal 5v regulator voltage output. the internal voltage regulator provides 5v to the mosfet driver and other internal circuits. vdrv is referenced to gnd. do not use vdrv to drive external circuits. connect a 1 f f bypass capacitor between vdrv and gnd. 8 8 sl sleep mode enable input. a falling edge on sl brings the device into sleep mode. an external resistor (r sl ) connected between sl and gnd sets the led current (i led ). 8 ldo_ fb ldo regulator feedback input. connect to vdrv to get the preset ldo output voltage of 3.3v, or connect to a resistive divider from the ldo_out to gnd for an adjustable ldo output voltage. 9 9 ulp ultra-low power-mode enable input. ulp has an internal 50k i pullup resistor to the internal 5v bias rail. a falling edge on sl while ulp is asserted low enables ultra-low power mode. when ultra-low power mode is enabled, the power consumption of the device is reduced even lower than sleep mode to comply with ultra-low power sleep power requirements while still supporting mps. 10 9 class2 class 2 selection input. connect to vdrv for class 2 operation. connect to gnd for class 1 operation. 11 10 mps mps enable input. connect to vdrv to turn the mps function on. connect to gnd to turn mps off. 11 reset open-drain reset output. the reset output is driven low if either ldo_out or fb drops below 90% of its set value. reset goes high 100 f s after both ldo_out and fb rise above 95% of their set values. leave unconnected when not used. 12 12 12 wad wall power adapter detector input. wall adapter detection is enabled when the voltage from wad to gnd is greater than 8.8v. when a wall power adapter is present, the isolation p-channel power mosfet turns off. connect wad directly to gnd when the wall power adapter or other auxiliary power source is not used. 13 13 13 v dd positive supply input. connect a 68nf (min) bypass capacitor between v dd and pgnd. 14 14 14 v cc dc-dc converter power input. v dd is connected to v cc by an isolation p-channel mosfet. connect a 10 f f capacitor in parallel with a 1 f f ceramic capacitor between v cc and pgnd. 15 15 15 pgnd power ground. power ground of the dc-dc converter power stage. connect pgnd to gnd with a star connection. do not use pgnd as reference for sensitive feedback circuit. 16 16 16 rref signature resistor connection. connect a 24.9k i resistor (r sig ) to gnd. ep exposed pad. connect the exposed pad to ground. max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
13 detailed description pd interface the max5986a/max5986b/MAX5987A include complete interface functions for a pd to comply with the ieee 802.3af standard as a class 1/class 2 pd. the devic - es provide the detection and classification signatures using a single external signature resistor. an integrated mosfet provides isolation from the buck converter when the pse has not applied power. the devices guarantee a leakage current offset of less than 10a during the detec - tion phase. the devices feature power-mode under - voltage-lockout (uvlo) with wide hysteresis and long deglitch time to compensate for twisted-pair-cable resis - tive drop and to ensure glitch-free transitions between detection, classification, and power-on/-off modes. operating modes the devices operate in three different modes depending on v dd . the three modes are detection mode, classifica - tion mode, and power mode. the device is in detection mode when v dd is between 1.4v and 10.1v, classifica - tion mode when v dd is between 12.6v and 20v, and power mode when the input voltage exceeds v on . detection mode (1.4v < v dd < 10.1v) in detection mode, the devices provide a signature differential resistance to v dd . during detection, the power-sourcing equipment (pse) applies two voltages to v dd , both between 1.4v and 10.1v with a minimum 1v increment. the pse computes the differential resistance to ensure the presence of the 24.9k signature resis - tor. connect the 24.9k signature resistor (r sig ) from rref to gnd for proper signature detection. the device applies v dd to rref when in detection mode, and the v dd offset current due to the device is less than 10a. the dc offset due to protection diodes does not signifi - cantly affect the signature resistance measurement. classification mode (12.6v < v dd < 20v) in classification mode, the devices sink class 1/class 2 classification currents. the pse applies a classification voltage between 12.6v and 20v, and measures the clas - sification currents. the devices use the external 24.9k resistor (r sig ) and the class2 pin to set the classifica - tion current at 10.5ma (class 1) or 18.5ma (class 2). the max5986a only provides the class 1 operation, while the max5986b/MAX5987A provide either class 1 (class2 = gnd) or class 2 (class2 = vdrv). the pse uses this to determine the maximum power to deliver. the classifica - tion current includes current drawn by the supply current of the device so the total current drawn by the pd is with - in the ieee 802.3af standard. the classification current is turned off when the device leaves classification mode. power mode (v dd > v on ) in power mode, the devices have the isolation mosfet between v dd and v cc fully on. the MAX5987A has the buck regulator enabled and the ldo enabled. the max5986a/max5986b can be in either wake mode, sleep mode, or ultra-low power mode. the buck regula - tor is enabled when the max5986a/max5986b is in wake mode. the devices enter power mode when v dd rises above the undervoltage lockout threshold (v on ). when v dd rises above v on , the device turns on the internal p-channel isolation mosfet to connect v cc to v dd with inrush current limit internally set to 49ma (typ). the iso - lation mosfet is fully turned on when v cc is near v dd and the inrush current is below the inrush limit. once the isolation mosfet is fully turned on, the device changes the current limit to 201ma (max5986a) or 323ma (max5986b/MAX5987A). the buck converter turns on 90ms (max5986a) or 116ms (max5986b/MAX5987A) after the isolation mosfet turns on fully. undervoltage lockout the devices operate with up to a 60v supply voltage with a turn-on uvlo threshold (v on ) at 35.4v/38.7v (typ), and a turn-off uvlo threshold (v off ) at 31.4v (typ). when the input voltage is above v on , the device enters power mode and the internal isolation mosfet is turned on. when the input voltage is below v off for more than t off_dly , the mosfet and the buck converter are off. led driver (max5986a/max5986b) the max5986a/max5986b drive an led, or multiple leds in series, with a maximum led voltage of 6.5v. in sleep mode and ultra-low power mode, the led cur - rent is pulse width modulated with a duty cycle of 25% and the amplitude is set by r sl . the led driver current amplitude is programmable from 10ma to 20ma using r sl according to the formula: i led = 646/r sl (ma) where r sl is in k. max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
14 sleep and ultra-low power modes (max5986a/max5986b) the max5986a/max5986b feature a sleep mode and an ultra-low power mode in which the internal p-channel isolation mosfet is kept on and the buck regulator is off. in sleep mode, the led driver output (led) pulse width modulates the led current with a 25% duty cycle. the peak led current (i led ) is set by an external resistor r sl . to enable sleep mode, apply a falling edge to sl with ulp disconnected or high impedance. sleep mode can only be entered from wake mode. ultra-low power mode allows the devices to reduce power consumption lower than sleep mode, while main - taining the power signature of the ieee standard. the ultra-low power-mode enable input ulp is internally held high with a 50k pullup resistor to the internal 5v bias of the device. to enable ultra-low power mode, apply a fall - ing edge to sl with ulp = low. ultra-low power mode can only be entered from wake mode. to exit from sleep mode or ultra-low power mode and resume normal operation, apply a falling edge on the wake-mode enable input ( wk ). thermal-shutdown protection if the devices die temperature reaches 143c, an over - temperature fault is generated and the device shuts down. the die temperature must cool down below +127c to remove the overtemperature fault condition. after a thermal shutdown condition clears, the device is reset. wad description for applications where an auxiliary power source such as a wall power adapter is used to power the pd, the devices feature wall power adapter detection. the wall power adapter is connected from wad to pgnd. the devices detect the wall power adapter when the volt - age from wad to pgnd is greater than 8.8v. when a wall power adapter is detected, the internal isolation mosfet is turned off, classification current is disabled. connect the auxiliar power source to wad, connect a diode from wad to v dd , and connect a diode from wad to v cc . see the typical application circuit in figure 2. the application circuit must ensure that the auxiliary power source can provide power to v dd and v cc by means of external diodes. the voltage on v dd must be within the v dd voltage range to allow the dc-dc to oper - ate. to allow operation of the dc-dc converter, the v dd and v cc voltage must be greater than 8.7v, on the rising edge, while on the falling edge the v dd and v cc may fall down to 7.3v keeping the dc-dc converter on. note: when operating solely with a wall power adapter, the wad voltage must be able to meet the condition v dd > 8.7v, that likely results in wad > 9.4v. internal linear regulator and back bias an internal voltage regulator provides vdrv to internal circuitry. the vdrv output is filtered by a 1f capaci - tor connected from vdrv to gnd. the regulator is for internal use only and cannot be used to provide power to external circuits. vdrv can be powered by either v dd or v aux , depending on v aux . the internal regulator is used for both pd and buck converter operations. v out can be used to back bias the vdrv voltage regu - lator if v out is greater than 4.75v. back biasing vdrv increases device efficiency by drawing current from v out instead of v dd . if v out is used as back bias, connect aux directly to v out . in this configuration, the v drv source switches from v dd to v aux after the buck converters output has reached its regulation voltage. cable discharge event protection (cde) a 70v voltage clamp is integrated to protect the internal circuits from a cable discharge event. dc-dc buck converter the dc-dc buck converter uses a pwm, peak current- mode, fixed-frequency control scheme providing an easy-to-implement architecture without sacrificing a fast transient response. the buck converter operates in a wide input voltage range from 8.7v to 60v and sup - ports up to 3.84w (max5986a) or 6.49w (max5986b/ MAX5987A) of input power. the devices provide a wide array of protection features including uvlo, overtemper - ature shutdown, short-circuit protection with hiccup run - away current limit, cycle-by-cycle peak current protec - tion, and cycle-by-cycle output overvoltage protection, for enhanced performance and reliability. a frequency foldback scheme is implemented to reduce the switching frequency to half at light loads to increase the efficiency. max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
15 frequency foldback protection for high-efficiency light-load operation the devices enter frequency foldback mode when eight consecutive inductor current zero-crossings occur. the switching frequency is 275khz or 214khz under loads large enough that the inductor current does not cross zero. in frequency foldback mode, the switching fre - quency is reduced to 137.5khz or 107khz to increase power conversion efficiency. the device returns to normal mode when the inductor current does not cross zero for eight consecutive switching periods. frequency foldback mode is forced during startup until 50% of the soft-start is completed. hiccup mode the devices include a hiccup protection feature. when hiccup protection is triggered, the devices turn off the high-side and turn on the low-side mosfet until the inductor current reaches the valley current limit. the control logic waits 120ms until attempting a new soft- start sequence. hiccup mode is triggered if the current in the high-side mosfet exceeds the runaway current- limit threshold, both during soft-start and during normal operating mode. hiccup mode can also be triggered in normal operating mode in the case of an output under - voltage event. this happens if the regulated feedback voltage drops below 60% (typ). reset output (MAX5987A) the MAX5987A features an open-drain reset output that indicates if either the ldo or the switching regula - tor drop out of regulation. the reset output goes low if either regulator drops below 92% of its regulated feed - back value. reset goes high impedance 100s after both regulators are above 95% of their value. maintain power signature (mps) the max5986b/MAX5987A feature the mps to comply to the ieee 802.3af standard. they are able to maintain a minimum current (10ma) of the port to avoid the power disconnection from the pse. the max5986b/MAX5987A enter the mps when the port current is lower than 14ma and also exit the mps mode when the port current is geater than 40ma. the feature is enabled by connecting the mps pin to vdrv, or disagbled by connecting the mps pin to gnd. applications information operation with wall adapter for applications where an auxiliary power source such as a wall power adapter is used to power the pd, the devices feature wall power adapter detection. the device gives priority to the wad supply over v dd supply, and smoothly switches the power supply to wad when it is detected. the wall power adapter is connected from wad to pgnd. the devices detect the wall power adapt - er when the voltage from wad to pgnd is greater than 8.8v. when a wall power adapter is detected, the internal isolation mosfet is turned off, classification current is disabled and the device draws power from the auxiliary power source through v cc . connect the auxiliary power source to wad, connect a diode from wad to v cc . see the typical application circuit in figure 2. adjusting ldo output voltage (MAX5987A) an uncommitted ldo regulator is available to provide a supply voltage to external circuits. a preset voltage of 3.3v is set by connecting ldo_fb directly to vdrv. for different output voltages connect a resistor divider from ldo_out and ldo_fb to gnd. the total feedback resistance should be in the range of 100k. the maxi - mum output current is 85ma and thermal considerations must be taken to prevent triggering thermal shutdown. the ldo regulator can be powered by vout, a differ - ent power supply, or grounded when not used. the ldo is enabled once the buck converter has reached the regulation voltage. the ldo is disabled when the buck converter is turned off or not regulating. adjusting buck converter output voltage the buck converter output voltage is set by changing the feedback resistor-divider ratio. the output voltage can be set from 3.0v to 5.6v (max5986a/MAX5987A) or 5.4v to 14v (max5986b). the fb voltage is regulated to 1.225v. keep the trace from the fb pin to the center of the resis - tive divider short, and keep the total feedback resistance around 100k. max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
16 inductor selection choose an inductor with the following equation: where lir is the ratio of the inductor ripple current to full load current at the minimum duty cycle. choose lir between 20% to 40% for best performance and stability. use an inductor with the lowest possible dc resistance that fits in the allotted dimensions. powdered iron ferrite core types are often the best choice for performance. with any core material, the core must be large enough not to saturate at the current limit of the devices. v cc input capacitor selection the input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the ic. the total input capacitance must be equal or greater than the value given by the following equation to keep the input-ripple voltage within specification and minimize the high-frequency ripple current being fed back to the input source: where v in-ripple is the maximum allowed input ripple voltage across the input capacitors and is recommended to be less than 2% of the minimum input voltage. d is the duty cycle (v out /v in ) and t s is the switching period (1/ f s ). the impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source, but are instead shunted through the input capacitor. the input capacitor must meet the ripple current requirement imposed by the switching currents. the rms input ripple current is given by: where i ripple is the input rms ripple current. output capacitor selection the key selection parameters for the output capacitor are capacitance, esr, esl, and voltage-rating requirements. these affect the overall stability, output ripple voltage, and transient response of the dc-dc converter. the out - put ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capaci - tors esr, and the voltage drop due to the capacitors esl. estimate the output-voltage ripple due to the output capacitance, esr, and esl: v ripple = v ripple(c) + v ripple(esr) +v ripple(esl) where the output ripple due to output capacitance, esr, and esl is: or whichever is larger. the peak-to-peak inductor current (i p-p ) use these equations for initial output capacitor selec - tion. determine final values by testing a prototype or an evaluation circuit. a smaller ripple current results in less output-voltage ripple. since the inductor ripple current is a factor of the inductor value, the output-voltage ripple decreases with larger inductance. use ceramic capaci - tors for low esr and low esl at the switching frequency of the converter. the ripple voltage due to esl is negli - gible when using ceramic capacitors. load-transient response depends on the selected output capacitance. during a load transient, the output instantly changes by esr x i load . before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. after a short time, the controller responds by regulating the output voltage back to its predetermined value. the controller response time depends on the closed-loop bandwidth. a higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value. max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
17 pcb layout careful pcb layout is critical to achieve clean and stable operation. it is highly recommended to duplicate the max5986a ev kit layout for optimum performance. if deviation is necessary, follow these guidelines for good pcb layout: 1) connect input and output capacitors to the power ground plane; connect all other capacitors to the sig - nal ground plane. 2) place capacitors on v dd , v cc , aux, v drv as close as possible to the ic and its corresponding pin using direct traces. keep power ground plane (connected to pgnd) and signal ground plane (connected to gnd) separate. 3) keep the high-current paths as short and wide as possible. keep the path of switching current short and minimize the loop area formed by lx, the output capacitors, and the input capacitors. 4) connect v dd , v cc , and pgnd separately to a large copper area to help cool the ic to further improve efficiency and long-term reliability. 5) ensure all feedback connections are short and direct. place the feedback resistors and compensation com - ponents as close as possible to the ic. 6) route high-speed switching nodes, such as lx, away from sensitive analog areas (fb). 7) place enough vias in the pad for the ep of the max5986a/max5986b/MAX5987A so that heat gener - ated inside can be effectively dissipated by the pcb copper. the recommended spacing for the vias is 1mm to 1.2mm pitch. the thermal vias should be plated (1oz copper) and have a small barrel diameter (0.3mm to 0.33mm). table 1. design selection table output c in c out l class 3.3v ceramic electrolytic ceramic 2.2 f f/100v 10 f f/63v 3x22 f f/6.3v 33 f h/1.4a 1 5v 2.2 f f/100v 10 f f/63v 3x22 f f/6.3v 47 f h/1.6a 1 or 2 12v 2.2 f f/100v 10 f f/63v 2x10 f f/16v 220 f /0.8a 1 or 2 max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
18 typical application circuits figure 3. max5986a 5v output with back bias max5986a vdrv v dd v cc wad wk sl rref gnd pgnd ulp aux lx fb led l0 47h c2 10f c1 68nf c3 1f 1f r1 75k i r sl 60.4k i 0 i to p open-drain outputs or pulldown switches r sig 24.9k i r2 24.9k i 5v output rj-45 and bridge rectifier c4 47f max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
19 typical application circuits (continued) figure 4. max5986b 5v output with back bias max5986b vdrv class2 mps v dd v cc wad wk sl rref gnd pgnd ulp aux lx fb led l0 47h c2 10f c1 68nf c3 1f 1f r1 75k i r sl 60.4k i 0 i to p open-drain outputs or pulldown switches r sig 24.9k i r2 24.9k i 5v output rj-45 and bridge rectifier c4 47f max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
20 typical application circuits (continued) figure 5. MAX5987A 5v buck regulator output and 3.3v ldo output MAX5987A ldo_fb v dd v cc wad rref gnd pgnd aux lx fb led l0 47h c2 10f c1 68nf c3 1f 1f r1 75k i 0 i r sig 24.9k i r2 24.9k i 5v output rj-45 and bridge rectifier vdrv to 5v output ldo_in c6 1f ldo_out c5 1f class2 mps c4 47f max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
21 functional diagram control clk 1.5v v ref driver fb pgnd lx vdrv aux wad v cc 5v hot-swap controller pd voltage monitor 5v 5v 1 0 5v 5v regulator open drain (MAX5987A only) (max5986a only) reset 5v detection classification tvs gnd v dd rref vref ldo_in ldo_out ldo_fb class2 mps ldo logic 50k i 50k i wk sl ulp led 5v v dd bandgap class mps max5986a max5986b MAX5987A v dd max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
22 ordering information chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. package type package code outline no. land pattern no. 16 tqfn-ep t1655-4 21-0140 90-0121 part pin-package sleep/ulp mode ldo uvlo (v) reset mps class2 max5986a ete+ 16 tqfn-ep* yes no 35.7 no no no max5986bete+ 16 tqfn-ep* yes no 35.7 no yes yes MAX5987A ete+ 16 tqfn-ep* no yes 38.7 yes yes yes max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 23 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/12 initial release 1 12/12 added max5986b and mps and class2 features 1C20 max5986a/max5986b/MAX5987A ieee 802.3af-compliant, high-efficiency, class 1/ class 2, pds with integrated dc-dc converter

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